View IDT85304_165385.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES:
* Five differential 3.3V LVPECL outputs * Selectable differential CLK, xCLK, or LVPECL clock inputs * CLK, xCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, and HCSL * PCLK, xPCLK supports the following input types: LVPECL, CML, and SSTL * Maximum output frequency: 650MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on xCLK input * Output skew: 35ps (max.) * Part-to-part skew: as low as 150ps * Propagation delay: 2.1ns (max.) * 3.3V operating supply * Available in TSSOP package
IDT85304-01
DESCRIPTION:
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT8530401 ideal for those applications that demand well-defined performance and repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
D Q
CLK xCLK PCLK xPCLK 1 0
LE Q0 xQ0 Q1 xQ1 Q2
CLK_SEL
xQ2 Q3 xQ3 Q4 xQ4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2004 Integrated Device Technology, Inc.
MAY 2004
DSC 6174/2
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Description Power Supply Voltage Input Voltage Output Voltage Package Thermal Impedance (0 lfpm) Storage Temperature Max 4.6 -0.5 to VDD+0.5 Unit V V VI VO
Q0 xQ0 Q1 xQ1 Q2 xQ2 Q3 xQ3 Q4 xQ4
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD CLK_EN VDD xPCLK PCLK VEE xCLK CLK CLK_SEL VDD
JA
TSTG
-0.5 to VDD+0.5 V 92.6 C/W -65 to +150 C
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN RPULLUP RPULLDOWN Description Input Capacitance Input Pullup Resistor Input Pulldown Resistor Typ. -- 51 51 Max. 4 -- -- Unit pF K K
TSSOP TOP VIEW
PIN DESCRIPTION(1)
Symbol xQ0, Q0 xQ1, Q1 xQ2, Q2 xQ3, Q3 xQ4, Q4 VDD CLK_SEL CLK xCLK VEE PCLK xPCLK CLK_EN Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 18, 20 12 13 14 15 16 17 19 Output Output Output Output Output Power Input Input Input Power Input Input Input Pulldown Pullup Pullup Pulldown Pulldown Pullup Type Description Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Positive Supply Pins Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects CLK / xCLK inputs. LVTTL / LVCMOS interface levels. Non-Inverting Differential Clock Input Inverting Differential Clock Input Negative Supply Pin Non-Inverting Differential LVPECL Clock Input Inverting Differential LVPECL Clock Input Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS interface levels.
NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE(1,2)
Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Selected Source CLK, xCLK PCLK, xPCLK CLK, xCLK PCLK, xPCLK Q0:Q4 Disabled; LOW Disabled; LOW Enabled Enabled Outputs xQ0:xQ4 Disabled; HIGH Disabled; HIGH Enabled Enabled
NOTES: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below. 2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Disabled CLK0, CLK1
Enabled

CLK_EN Timing Diagram
CLK EN
xQ0, xQ1, xQ2, xQ3, xQ4 Q0, Q1, Q2, Q3, Q4
CLOCK INPUT FUNCTION TABLE(1)
Inputs CLK or PCLK 0 1 0 1 Biased(2) Biased(2) xCLK or xPCLK 1 0 Biased 0 1
(2)
Outputs Q0:Q4 L H L H H L xQ0:xQ4 H L H L L H Input to Output Mode Differential to Differential Differential to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting
Biased(2)
NOTES: 1. H = HIGH L = LOW 2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
3
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol VDD IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Min. 3.135 -- Typ. 3.3 -- Max. 3.465 55 Unit V mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL
Symbol VIH VIL IIH IIL Parameter Input Voltage, HIGH Input Voltage, LOW Input Current HIGH Input Current LOW CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN CLK_SEL CLK_EN CLK_SEL VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 5 150 A A -0.3 0.8 V Test Conditions Min. 2 Typ. Max. VDD + 0.3 Unit V
DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL
Symbol VPP VCMR IIH IIL Parameter Peak-to-Peak Input Voltage Common Mode Input Voltage Input Current HIGH Input Current LOW
(1,2)
Test Conditions
Min. 0.15 0.5
Typ.
Max. 1.3 VDD - 0.85 5 150
Unit V V A A
xCLK CLK xCLK CLK
VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5
NOTES: 1. For single-ended applications, the max. input voltage for CLK / xCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH.
DC ELECTRICAL CHARACTERISTICS, LVPECL
Symbol IIH IIL VPP VCMR VOH VOL VSWING Parameter Input Current HIGH Input Current LOW PCLK xPCLK PCLK xPCLK Peak-to-Peak Input Voltage Common Mode Input Voltage Output Voltage HIGH(3) Output Voltage LOW(3) Peak-to-Peak Output Voltage Swing
(1,2)
Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V
Min.
Typ.
Max. 150 5
Unit A A
-5 -150 0.15 VEE + 1.5 VDD - 1.4 VDD - 2 0.6 1.3 VDD VDD - 1 VDD - 1.7 0.85
V V V V V
NOTES: 1. For single-ended applications, the max. input voltage for PCLK / xPCLK is VDD + 0.3V. 2. Common mode voltage is defined as VIH. 3. Outputs terminated with 50 to VDD - 0.2V.
4
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
All parameters measured at 500MHz unless noted otherwise; Cycle-to-cycle jitter = jitter on output; the part does not add jitter
Symbol FMAX tPD tSK(O) tSK(PP) tR tF odc Parameter Output Frequency Propagation Delay(1) Output Skew
(2,4) (3,4)
Test Conditions f 650MHz
Min. 1
Typ.
Max. 650 2.1 35 150
Unit MHz ns ps ps ps ps %
Part-to-Part Skew Output Rise Time Output Fall Time
20 - 80% @ 50MHz 20 - 80% @ 50MHz
300 300 48 50
700 700 52
Output Duty Cycle
NOTES: 1. Measured from the differential input crossingpoint to the differential output crossingpoint. 2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. This parameter is defined in accordance with JEDEC Standard 65.
5
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
VDD Scope Z = 50 Qx 50 Z = 50
LVPECL
VDD = 2V xQx
50
VEE = -1.3V 0.135V
Output Load Test Circuit
VDD
xCLK, xPCLK VPP CLK, PCLK
Cross Points
VCMR
VEE
Differential Input Level
xQx Qx
xQy Qy tSK(0)
Output Skew 6
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION - CONTINUED
80% 80% VSWING 20% 20%
Clock Outputs
tR
Input and Output Rise and Fall Time
tF
xCLK, xPLK CLK, PCLK
xQ0, xQ1, xQ2, xQ3, xQ4 Q0, Q1, Q2, Q3, Q4 tPD
Propagation Delay
xQ0, xQ1, xQ2, xQ3, xQ4 Q0, Q1, Q2, Q3, xQ4 Pulse Width tPERIOD tW odc = tPERIOD
odc and tPERIOD 7
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF VDD/2 is generated by the bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/ R1 = 0.609.
VDD
R1 1K
CLK_IN VREF
+ -
C1 0.1uF
R2 1K
Single-Ended Signal Driving Differential Input TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
5 2
FOUT Zo = 50 FIN
Zo
5 2
Zo
Zo = 50
FOUT
50 50
FIN Zo = 50
VDD - 2V 1 RTT = (VOH + VOL / VDD - 2) - 2 Zo RTT
3 2
Zo
3 2
Zo
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
8
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the IDT85304-01. Equations and example calculations are also provided. POWER DISSIPATION: The total power dissipation for the IDT85304-01is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating power dissipated in the load. Power (core)MAX = VDD_MAX * IEE_MAX = 3.465 * 55mA = 190.57mW Power (outputs)MAX = 30.2mW/Loaded Output Pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW JUNCTION TEMPERATURE: Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum recommended junction temperature for this device is 125C. The equation for is as follows: tJ = JA * Pd_total + TA tJ = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (JA) must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 77.6C/W per the following Thermal Resistance table. Therefore, tJ for an ambient temperature of 70C with all its outputs switching is: 70C + 0.341W * 77.6C/W = 96.46C. This is well below the limit of 125C. This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (singlelayer or multi-layer).
THERMAL RESISTANCE
JA for 20-pin TSSOP, forced convenction JA by Velocity (Linear Feet per mInute)
0 Multi-Layer PCB, JEDEC Standard Test boards 92.6 200 77.6 400 70.9 Unit
C/W
9
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CALCULATIONS AND EQUATIONS
VDD
Q1
VOUT RL 50 VDD - 2V
LVPECL Output Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations, which assume a 50 load and a termination voltage of VDD - 2V. For Logic HIGH: VOUT = VOH_MAX = VDD_MAX - 1V. (VDD_MAX - VOH_MAX) = 1V For Logic LOW: VOUT = VOL_MAX = VDD_MAX - 1.7V. (VDD_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives HIGH. Pd_L is power dissipation when the output drives LOW. Pd_H = {[ VOH_MAX - (VDD_MAX - 2V)] / RL} * (VDD_MAX - VOH_MAX) = {[ 2V - (VDD_MAX - VOH_MAX)] / RL} * (VDD_MAX - VOH_MAX) = [( 2V - 1V) / 50] * 1V = 20mW. Pd_L = {[ VOL_MAX - (VDD_MAX - 2V)] / RL} * (VDD_MAX - VOL_MAX) = {[ 2V - (VDD_MAX - VOL_MAX)] / RL} * (VDD_MAX - VOL_MAX) = [( 2V - 1.7V) / 50] * 1.7V = 10.2mW. Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
10
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
C I
Commercial (0C to +70C) Industrial (-40C to +85C)
PG
Thin Shrink Small Outline Package
85304-01
Low Skew, 1-to-5 Differential-to-3.3V LVPECL Fanout Buffer
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 11
for Tech Support: logichelp@idt.com (408) 654-6459

▲Up To Search▲

Price & Availability of IDT85304

	To Download IDT85304 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .